\doxysection{CEC\+\_\+\+Type\+Def Struct Reference}
\hypertarget{struct_c_e_c___type_def}{}\label{struct_c_e_c___type_def}\index{CEC\_TypeDef@{CEC\_TypeDef}}


Consumer Electronics Control.  




{\ttfamily \#include $<$stm32h723xx.\+h$>$}

\doxysubsubsection*{Public Attributes}
\begin{DoxyCompactItemize}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_c_e_c___type_def_ab272f34d3acb1edeaaeaf087b284d77f}{CR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_c_e_c___type_def_a91a55cd277c20e5c5ad228fd9013d014}{CFGR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_c_e_c___type_def_ab8d8a4703a2a87dcd4d1d7b1f38bd464}{TXDR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_c_e_c___type_def_ae2bc7566d4fe07776fc8e5b2ace32981}{RXDR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_c_e_c___type_def_ae4e736a0aa1304172139d21b9d75c08a}{ISR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_c_e_c___type_def_acbba4df34183910fdc40fb2c4918e303}{IER}}
\end{DoxyCompactItemize}


\doxysubsection{Detailed Description}
Consumer Electronics Control. 

\label{doc-variable-members}
\Hypertarget{struct_c_e_c___type_def_doc-variable-members}
\doxysubsection{Member Data Documentation}
\Hypertarget{struct_c_e_c___type_def_a91a55cd277c20e5c5ad228fd9013d014}\index{CEC\_TypeDef@{CEC\_TypeDef}!CFGR@{CFGR}}
\index{CFGR@{CFGR}!CEC\_TypeDef@{CEC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{CFGR}{CFGR}}
{\footnotesize\ttfamily \label{struct_c_e_c___type_def_a91a55cd277c20e5c5ad228fd9013d014} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t CEC\+\_\+\+Type\+Def\+::\+CFGR}

CEC configuration register, Address offset\+:0x04 \Hypertarget{struct_c_e_c___type_def_ab272f34d3acb1edeaaeaf087b284d77f}\index{CEC\_TypeDef@{CEC\_TypeDef}!CR@{CR}}
\index{CR@{CR}!CEC\_TypeDef@{CEC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{CR}{CR}}
{\footnotesize\ttfamily \label{struct_c_e_c___type_def_ab272f34d3acb1edeaaeaf087b284d77f} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t CEC\+\_\+\+Type\+Def\+::\+CR}

CEC control register, Address offset\+:0x00 \Hypertarget{struct_c_e_c___type_def_acbba4df34183910fdc40fb2c4918e303}\index{CEC\_TypeDef@{CEC\_TypeDef}!IER@{IER}}
\index{IER@{IER}!CEC\_TypeDef@{CEC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{IER}{IER}}
{\footnotesize\ttfamily \label{struct_c_e_c___type_def_acbba4df34183910fdc40fb2c4918e303} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t CEC\+\_\+\+Type\+Def\+::\+IER}

CEC interrupt enable register, Address offset\+:0x14 \Hypertarget{struct_c_e_c___type_def_ae4e736a0aa1304172139d21b9d75c08a}\index{CEC\_TypeDef@{CEC\_TypeDef}!ISR@{ISR}}
\index{ISR@{ISR}!CEC\_TypeDef@{CEC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{ISR}{ISR}}
{\footnotesize\ttfamily \label{struct_c_e_c___type_def_ae4e736a0aa1304172139d21b9d75c08a} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t CEC\+\_\+\+Type\+Def\+::\+ISR}

CEC Interrupt and Status Register, Address offset\+:0x10 \Hypertarget{struct_c_e_c___type_def_ae2bc7566d4fe07776fc8e5b2ace32981}\index{CEC\_TypeDef@{CEC\_TypeDef}!RXDR@{RXDR}}
\index{RXDR@{RXDR}!CEC\_TypeDef@{CEC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{RXDR}{RXDR}}
{\footnotesize\ttfamily \label{struct_c_e_c___type_def_ae2bc7566d4fe07776fc8e5b2ace32981} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t CEC\+\_\+\+Type\+Def\+::\+RXDR}

CEC Rx Data Register, Address offset\+:0x0C \Hypertarget{struct_c_e_c___type_def_ab8d8a4703a2a87dcd4d1d7b1f38bd464}\index{CEC\_TypeDef@{CEC\_TypeDef}!TXDR@{TXDR}}
\index{TXDR@{TXDR}!CEC\_TypeDef@{CEC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{TXDR}{TXDR}}
{\footnotesize\ttfamily \label{struct_c_e_c___type_def_ab8d8a4703a2a87dcd4d1d7b1f38bd464} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t CEC\+\_\+\+Type\+Def\+::\+TXDR}

CEC Tx data register , Address offset\+:0x08 

The documentation for this struct was generated from the following file\+:\begin{DoxyCompactItemize}
\item 
C\+:/\+Users/\+ASUS/\+Desktop/dm-\/ctrl\+H7-\/balance-\/9025test/\+Drivers/\+CMSIS/\+Device/\+ST/\+STM32\+H7xx/\+Include/\mbox{\hyperlink{stm32h723xx_8h}{stm32h723xx.\+h}}\end{DoxyCompactItemize}
